[Intel-gfx] [PATCH 11/12] drm/i915: Use flush_work to synchronize with dmc loader

[Daniel Vetter]

I have just placed them at the exact spot the old code had a
set_state. This probably needs to be moved earlier into the suspend
sequence, but I didn't audit that.

FIXME:
- Do this audit and move the flush_work to the right places.
- For consistency and since we have the work already it would be nice
  to also load the dmc asynchronously on resume. We can reuse the same
  loader function by simply skipping the fw loading&parsing when
  dev_priv->csr.dmc_payload is set already.

Cc: Animesh Manna <animesh.manna at intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c  | 2 +-
 drivers/gpu/drm/i915/intel_csr.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7dfe9136c86f..2764f3520c2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -997,7 +997,7 @@ static int i915_pm_resume(struct device *dev)
 
 static int skl_suspend_complete(struct drm_i915_private *dev_priv)
 {
-	/* Enabling DC6 is not a hard requirement to enter runtime D3 */
+	flush_work(&dev_priv->csr.work);
 
 	skl_uninit_cdclk(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 58ff765dc9b5..350b36f1237b 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -402,5 +402,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 	if (!HAS_CSR(dev_priv))
 		return;
 
+	flush_work(&dev_priv->csr.work);
+
 	kfree(dev_priv->csr.dmc_payload);
 }
-- 
2.1.4