[Intel-gfx] [PATCH] drm/i915: Adjust BXT HDMI port clock limits

[Daniel Vetter]

On Fri, Jul 10, 2015 at 04:09:42PM +0300, Imre Deak wrote:
> On ma, 2015-07-06 at 14:44 +0300, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Since
> >  commit e62925567c7926e78bc8ca976cde5c28ea265a49
> >  Author: Vandana Kannan <vandana.kannan at intel.com>
> >  Date:   Wed Jul 1 17:02:57 2015 +0530
> > 
> >     drm/i915/bxt: BUNs related to port PLL
> > 
> > BXT DPLL can now generate frequencies in the 216-223 MHz range.
> > Adjust the HDMI port clock checks to account for the reduced range
> > of invalid frequencies.
> > 
> > Cc: Vandana Kannan <vandana.kannan at intel.com>
> > Cc: Imre Deak <imre.deak at intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Ville wrote a tool for CHV that calculates the valid frequencies based
> on the algorithm in the kernel. With the help of that I verified that
> this matches the list of target frequencies bxt_find_best_dpll() will
> accept, so:
> Reviewed-by: Imre Deak <imre.deak at intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch