[Intel-gfx] [PATCH 5/6] drm/i915: check for the supported strides on HSW+ FBC
Paulo Zanoni
przanoni at gmail.com
Tue Jul 14 11:55:45 PDT 2015
2015-07-09 14:28 GMT-03:00 Paulo Zanoni <przanoni at gmail.com>:
> 2015-07-09 14:15 GMT-03:00 Daniel Vetter <daniel at ffwll.ch>:
>> Plus igt testcases to make sure we check for this (since
>> right now it seems like we don't).
>
> It's on the TODO list but it's not a priority since the Kernel checks
> are very straightforward. One of the problems is that different
> platforms have different requirements, so I'll have to hardcode those
> requirements on IGT too. And I'll have to stop using igt_create_fb for
> that case since it only use powers of 2 for stride.
>
> So yeah, one day we may have the test, but not a priority right now
> since it's very easy to look at the Kernel code and make sure it's
> correct.
Ok, so I implemented fbc-badstride with the restrictions mentioned in
this patch:
http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/commit/?id=cb3861a9e3f1bc12765160345bb0dd1d543f5086
If we add more restrictions we'll have to update the test.
>
>> Additional checks here in the fbc code
>> don't seem required. But if you want to I guess you could convert them to
>> WARN_ON (without bailing out).
>> -Daniel
>>
>>> + (fb->pitches[0] & (64 - 1)) != 0) {
>>> + set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE);
>>> + goto out_disable;
>>> + }
>>> +
>>> /* If the kernel debugger is active, always disable compression */
>>> if (in_dbg_master()) {
>>> set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER);
>>> --
>>> 2.1.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>
>
>
> --
> Paulo Zanoni
--
Paulo Zanoni
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