[Intel-gfx] [PATCH 13/16] drm/i915: Add DeGamma correction for CHV/BSW
Kausal Malladi
Kausal.Malladi at intel.com
Wed Jul 15 06:09:37 PDT 2015
CHV/BSW supports DeGamma color correction feature, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
CHV/BSW platform
2. Adds DeGamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
Signed-off-by: Kausal Malladi <Kausal.Malladi at intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 ++
drivers/gpu/drm/i915/intel_color_manager.c | 122 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 6 ++
3 files changed, 133 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ec2e4f..b95862e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7913,9 +7913,14 @@ enum skl_disp_power_wells {
#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000)
#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000)
#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000)
+#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
+#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
+#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000)
#define _PIPE_CGM_CONTROL(pipe) \
(_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL))
#define _PIPE_GAMMA_BASE(pipe) \
(_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA))
+#define _PIPE_DEGAMMA_BASE(pipe) \
+ (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA))
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 908b7ed..121ec43 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,121 @@
#include "intel_color_manager.h"
+int chv_set_degamma(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ struct drm_palette *degamma_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_mode_config *config = &dev->mode_config;
+ u32 cgm_control_reg = 0;
+ u32 cgm_degamma_reg = 0;
+ enum pipe pipe;
+ u32 red, green, blue;
+ u8 red_int, green_int, blue_int;
+ u16 red_fract, green_fract, blue_fract;
+ u32 count = 0;
+ struct drm_r32g32b32 *correction_values = NULL;
+ u32 num_samples;
+ u32 word;
+ int ret = 0, length;
+
+ if (!blob) {
+ DRM_ERROR("NULL Blob\n");
+ return -EINVAL;
+ }
+
+ degamma_data = (struct drm_palette *)blob->data;
+
+ if (degamma_data->version != CHV_DEGAMMA_DATA_STRUCT_VERSION) {
+ DRM_ERROR("Invalid DeGamma Data struct version\n");
+ return -EINVAL;
+ }
+
+ pipe = to_intel_crtc(crtc)->pipe;
+ num_samples = degamma_data->num_samples;
+ length = num_samples * sizeof(struct drm_r32g32b32);
+
+ if (num_samples == 0) {
+
+ /* Disable DeGamma functionality on Pipe - CGM Block */
+ cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe));
+ cgm_control_reg &= ~CGM_DEGAMMA_EN;
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg);
+
+ DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ } else if (num_samples == CHV_DEGAMMA_MAX_VALS) {
+ cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe);
+
+ count = 0;
+ correction_values = (struct drm_r32g32b32 *)°amma_data->lut;
+ while (count < CHV_DEGAMMA_MAX_VALS) {
+ blue = correction_values[count].b32;
+ green = correction_values[count].g32;
+ red = correction_values[count].r32;
+
+ blue_int = _GAMMA_INT_PART(blue);
+ if (blue_int > GAMMA_INT_MAX)
+ blue = CHV_MAX_GAMMA;
+ green_int = _GAMMA_INT_PART(green);
+ if (green_int > GAMMA_INT_MAX)
+ green = CHV_MAX_GAMMA;
+ red_int = _GAMMA_INT_PART(red);
+ if (red_int > GAMMA_INT_MAX)
+ red = CHV_MAX_GAMMA;
+
+ blue_fract = _GAMMA_FRACT_PART(blue);
+ green_fract = _GAMMA_FRACT_PART(green);
+ red_fract = _GAMMA_FRACT_PART(red);
+
+ blue_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+ green_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+ red_fract >>= CHV_DEGAMMA_MSB_SHIFT;
+
+ /* Green (29:16) and Blue (13:0) in DWORD1 */
+ word = green_fract;
+ word <<= CHV_DEGAMMA_GREEN_SHIFT;
+ word = word | blue;
+ I915_WRITE(cgm_degamma_reg, word);
+
+ cgm_degamma_reg += 4;
+
+ /* Red (13:0) to be written to DWORD2 */
+ word = red_fract;
+ I915_WRITE(cgm_degamma_reg, word);
+
+ cgm_degamma_reg += 4;
+ count++;
+ }
+
+ DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n",
+ pipe_name(pipe));
+
+ /* Enable DeGamma on Pipe */
+ I915_WRITE(_PIPE_CGM_CONTROL(pipe),
+ I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_DEGAMMA_EN);
+
+ DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n",
+ pipe_name(pipe));
+ ret = 0;
+ } else {
+ DRM_ERROR("Invalid number of samples for DeGamma LUT\n");
+ return -EINVAL;
+ }
+
+ ret = drm_property_replace_global_blob(dev, &blob, length,
+ (void *) degamma_data, &crtc->base,
+ config->prop_palette_before_ctm);
+
+ if (ret) {
+ DRM_ERROR("Error updating DeGamma blob\n");
+ return -EFAULT;
+ }
+
+ return ret;
+}
+
int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob,
struct drm_crtc *crtc)
{
@@ -173,6 +288,13 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
"Gamma registers Commit success!\n");
}
+ blob = crtc_state->palette_before_ctm_blob;
+ if (blob) {
+ ret = chv_set_degamma(dev, blob, crtc);
+ if (!ret)
+ DRM_DEBUG_DRIVER(
+ "DeGamma registers Commit success!\n");
+ }
}
}
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 8bbac20..6a4fff2 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -49,5 +49,11 @@
/* Max value for Gamma on CHV */
#define CHV_MAX_GAMMA 0x10000
+/* DeGamma correction */
+#define CHV_DEGAMMA_DATA_STRUCT_VERSION 1
+#define CHV_DEGAMMA_MSB_SHIFT 2
+#define CHV_DEGAMMA_GREEN_SHIFT 16
+
/* CHV CGM Block */
#define CGM_GAMMA_EN (1 << 2)
+#define CGM_DEGAMMA_EN (1 << 0)
--
2.4.5
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