[Intel-gfx] [PATCH 3/3] drm/i915: kerneldoc for fences

[Chris Wilson]

On Fri, Jul 24, 2015 at 01:55:12PM +0200, Daniel Vetter wrote:
> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com>
> ---
>  Documentation/DocBook/drm.tmpl        |  5 +++
>  drivers/gpu/drm/i915/i915_gem_fence.c | 75 +++++++++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
> index 458772e6ce08..86c9c453b218 100644
> --- a/Documentation/DocBook/drm.tmpl
> +++ b/Documentation/DocBook/drm.tmpl
> @@ -4137,6 +4137,11 @@ int num_ioctls;</synopsis>
>  !Idrivers/gpu/drm/i915/i915_gem_gtt.c
>        </sect2>
>        <sect2>
> +        <title>Global GTT Fence Handling</title>
> +!Pdrivers/gpu/drm/i915/i915_gem_fence.c fence handling
> +!Idrivers/gpu/drm/i915/i915_gem_fence.c
> +      </sect2>
> +      <sect2>
>          <title>Buffer Object Eviction</title>
>  	<para>
>  	  This section documents the interface functions for evicting buffer
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index d3284ee04794..63d8d0d8a9cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -25,6 +25,36 @@
>  #include <drm/i915_drm.h>
>  #include "i915_drv.h"
>  
> +/**
> + * DOC: fence handling

DOC: fence register handling

Might as well aim not to be ambiguous when you start out by pointing out
the confusion between the GTT detiling registers and dma-fence.

> + *
> + * Important to avoid confusions: "fences" in the i915 driver are not execution
> + * fences used to track command completion but hardware detiler objects which
> + * wrap a given range of the global GTT. Each platform has only a fairly limited
> + * set of these objects.

Hmm, good point. Maybe i915_gem_tiling was the better name after all!
Otoh, i915_gem_fence is better as it prevents us from wondering whether
this is suitable for Yf etc.

We really should emphasize that again in the set-tiling documentation -
that is not about declaring the tiling for the buffer per-se, but about
fence allocation.

> + *
> + * Fences are used to detile GTT memory mappings. They're also connected to the
> + * hardware frontbuffer render tracking and hence interract with frontbuffer
> + * conmpression. Furthermore on older platforms fences are required for tiled
> + * objects used by the display engine. They can also be used by the render
> + * engine - they're required for blitter commands and are optional for render
> + * commands. But on gen4+ both display (with the exception of fbc) and rendering
> + * have their own tiling state bits and don't need fences.
> + *
> + * Also note that fences only support X and Y tiling and hence can't be used for
> + * the fancier new tiling formats like W, Ys and Yf.
> + *
> + * Finally note that because fences are such a restricted resource they're
> + * dynamically associated with objects. Furthermore fence state is committed to
> + * the hardware lazily to avoid unecessary stalls on gen2/3. Therefore code must
> + * explictly call i915_gem_object_get_fence() to synchronize fencing status
> + * for cpu access. Also note that some code wants an unfenced view, for those
> + * cases the fence can be removed forcefully with i915_gem_object_put_fence().
> + *
> + * Internally these functions will synchronize with userspace access by removing
> + * ptes as needed.

Revoking CPU ptes into GTT mmaps.

Important when discussing PTEs to be clear when we don't mean the GTT
PTEs (which I think is the default for the driver).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre