[Intel-gfx] [PATCH 14/18] drm/i915/gen9: Use flush_work to synchronize with dmc loader

[Animesh Manna]

As power well 1 is superset of power well 2 and always pw2
will be disabled first and then pw1. On the other hand dmc
is responsible to save & restore back pw1 when display
engine goes and come back from low power state. Before
disabling pw1 dmc must be loaded, so adding flush_work()
while disabling pw2 which ensure that firmware will be
available before disabling pw1 in suspend flow.

Cc: Daniel Vetter <daniel.vetter at intel.com>
Cc: Damien Lespiau <damien.lespiau at intel.com>
Cc: Imre Deak <imre.deak at intel.com>
Cc: Sunil Kamath <sunil.kamath at intel.com>
Signed-off-by: Animesh Manna <animesh.manna at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 2 --
 drivers/gpu/drm/i915/intel_csr.c        | 2 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 98343eb..ddf8a25 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -995,8 +995,6 @@ static int i915_pm_resume(struct device *dev)
 
 static int skl_suspend_complete(struct drm_i915_private *dev_priv)
 {
-	/* Enabling DC6 is not a hard requirement to enter runtime D3 */
-
 	skl_uninit_cdclk(dev_priv);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 36386324..1858f02 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -417,5 +417,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 	if (!HAS_CSR(dev_priv))
 		return;
 
+	flush_work(&dev_priv->csr.work);
+
 	kfree(dev_priv->csr.dmc_payload);
 }
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f1ae23..a5059e8 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -652,6 +652,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 
 			if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 				power_well->data == SKL_DISP_PW_2) {
+				flush_work(&dev_priv->csr.work);
 				if (SKL_ENABLE_DC6(dev))
 					skl_enable_dc6(dev_priv);
 				else
-- 
2.0.2