[Intel-gfx] [PATCH v5 07/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support

[Michel Thierry]

On 7/16/2015 10:33 AM, Michel Thierry wrote:
> In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
> the base address to PML4, while the other PDP registers are ignored.
>
> In LRC, the addressing mode must be specified in every context
> descriptor, and the base address to PML4 is stored in the reg state.
>
> v2: PML4 update in legacy context switch is left for historic reasons,
> the preferred mode of operation is with lrc context based submission.
> v3: s/gen8_map_page_directory/gen8_setup_page_directory and
> s/gen8_map_page_directory_pointer/gen8_setup_page_directory_pointer.
> Also, clflush will be needed for bxt. (Akash)
> v4: Squashed lrc-specific code and use a macro to set PML4 register.
> v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
> PDP update in bb_start is only for legacy 32b mode.
> v6: Rebase after final merged version of Mika's ppgtt/scratch
> patches.
> v7: There is no need to update the pml4 register value in
> execlists_update_context (Akash)
>
> Cc: Akash Goel <akash.goel at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> Signed-off-by: Michel Thierry <michel.thierry at intel.com> (v2+)
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++++++++++++++++++++++++++++----
>   drivers/gpu/drm/i915/i915_gem_gtt.h |  2 ++
>   drivers/gpu/drm/i915/i915_reg.h     |  1 +
>   drivers/gpu/drm/i915/intel_lrc.c    | 60 ++++++++++++++++++++++++++-----------
>   4 files changed, 94 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 5901810..8bcd328 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -210,6 +210,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
>          return pde;
>   }
>
> +#define gen8_pdpe_encode gen8_pde_encode
> +#define gen8_pml4e_encode gen8_pde_encode
> +
>   static gen6_pte_t snb_pte_encode(dma_addr_t addr,
>                                   enum i915_cache_level level,
>                                   bool valid, u32 unused)
> @@ -599,6 +602,35 @@ static void free_pdp(struct drm_device *dev,
>          }
>   }
>
> +static void
> +gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
> +                         struct i915_page_directory_pointer *pdp,
> +                         struct i915_page_directory *pd,
> +                         int index)
> +{
> +       gen8_ppgtt_pdpe_t *page_directorypo;
> +
> +       if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
> +               return;
> +
> +       page_directorypo = kmap_px(pdp);
> +       page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
> +       kunmap_px(ppgtt, page_directorypo);
> +}
> +
> +static void
> +gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
> +                                 struct i915_pml4 *pml4,
> +                                 struct i915_page_directory_pointer *pdp,
> +                                 int index)
> +{
> +       gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
> +
> +       WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
> +       pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
> +       kunmap_px(ppgtt, pagemap);
> +}
> +
>   /* Broadwell Page Directory Pointer Descriptors */
>   static int gen8_write_pdp(struct drm_i915_gem_request *req,
>                            unsigned entry,

These _setup_ functions don't belong to this patch, and should be moved 
to the previous one in the patchset ("drm/i915/gen8: implement 
alloc/free for 4lvl").