[Intel-gfx] [PATCH] drm/i915: remove intermediate link rate entries for CHV
Sivakumar Thulasimani
sivakumar.thulasimani at intel.com
Thu Jul 30 03:28:42 PDT 2015
On 7/30/2015 3:31 PM, Jani Nikula wrote:
> On Thu, 30 Jul 2015, Sivakumar Thulasimani <sivakumar.thulasimani at intel.com> wrote:
>> From: "Thulasimani,Sivakumar" <sivakumar.thulasimani at intel.com>
>>
>> CHV does not support intermediate link rates nor does it support
>> HBR2. This patch removes those entries and returns HBR as the max
>> link rate supported on CHV platform.
> These are two separate changes, and should be two separate
> patches. Moreover, the intermediate link rate change should be a revert
> of
>
> commit fe51bfb95c996733150c44d21e1c9f4b6322a326
> Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Date: Thu Mar 12 17:10:38 2015 +0200
>
> drm/i915: Add eDP intermediate frequencies for CHV
>
> with Cc: Ville and Sonika to record this back and forth here.
>
> BR,
> Jani.
Sure, will share new patch that will revert the above one and create a
new patch
for restricting CHV to HBR.
>
>> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani at intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 11 +++--------
>> 1 file changed, 3 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 898dc74..5c68b17 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> 324000, 432000, 540000 };
>> static const int skl_rates[] = { 162000, 216000, 270000,
>> 324000, 432000, 540000 };
>> -static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> - 243000, 270000, 324000, 405000,
>> - 420000, 432000, 540000 };
>> static const int default_rates[] = { 162000, 270000, 540000 };
>>
>> /**
>> @@ -1186,15 +1183,13 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>> } else if (IS_SKYLAKE(dev)) {
>> *source_rates = skl_rates;
>> return ARRAY_SIZE(skl_rates);
>> - } else if (IS_CHERRYVIEW(dev)) {
>> - *source_rates = chv_rates;
>> - return ARRAY_SIZE(chv_rates);
>> }
>>
>> *source_rates = default_rates;
>>
>> - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
>> - /* WaDisableHBR2:skl */
>> + /* WaDisableHBR2:skl */
>> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
>> + IS_CHERRYVIEW(dev))
>> return (DP_LINK_BW_2_7 >> 3) + 1;
>> else if (INTEL_INFO(dev)->gen >= 8 ||
>> (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
regards,
Sivakumar
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