[Intel-gfx] [PATCH 07/21] drm/i915/gtt: Introduce i915_page_dir_dma_addr

[Michel Thierry]

On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
> The legacy mode mm switch and the execlist context assignment
> needs dma address for the page directories.
>
> Introduce a function that encapsulates the scratch_pd dma
> fallback if no pd is found.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>

Reviewed-by: Michel Thierry <michel.thierry at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++----
>   drivers/gpu/drm/i915/i915_gem_gtt.h | 8 ++++++++
>   drivers/gpu/drm/i915/intel_lrc.c    | 4 +---
>   3 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4cf47f9..18989f7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -481,10 +481,8 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
>          int i, ret;
>
>          for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
> -               struct i915_page_directory *pd = ppgtt->pdp.page_directory[i];
> -               dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr;
> -               /* The page directory might be NULL, but we need to clear out
> -                * whatever the previous context might have used. */
> +               const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
> +
>                  ret = gen8_write_pdp(ring, i, pd_daddr);
>                  if (ret)
>                          return ret;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index c343161..da67542 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -468,6 +468,14 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
>          return i915_pte_count(address, length, GEN8_PDE_SHIFT);
>   }
>
> +static inline dma_addr_t
> +i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
> +{
> +       return test_bit(n, ppgtt->pdp.used_pdpes) ?
> +               ppgtt->pdp.page_directory[n]->daddr :
> +               ppgtt->scratch_pd->daddr;
> +}
> +
>   int i915_gem_gtt_init(struct drm_device *dev);
>   void i915_gem_init_global_gtt(struct drm_device *dev);
>   void i915_global_gtt_cleanup(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d793d4e..626949a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -184,9 +184,7 @@
>   #define CTX_GPGPU_CSR_BASE_ADDRESS     0x44
>
>   #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
> -       const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
> -               ppgtt->pdp.page_directory[n]->daddr : \
> -               ppgtt->scratch_pd->daddr; \
> +       const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
>          reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
>          reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
>   }
> --
> 1.9.1
>
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