[Intel-gfx] [PATCH] drm/i915: Initialize HWS page address after GPU reset

[Ville Syrjälä]

On Tue, Jun 02, 2015 at 08:06:59PM +0100, Arun Siluvery wrote:
> After GPU reset, HW is losing the address of HWS page in the register.
> The page itself is valid except that HW is not aware of its location.
> 
> [   64.368623] [drm:gen8_init_common_ring [i915]] *ERROR* HWS Page address = 0x00000000
> [   64.368655] [drm:gen8_init_common_ring [i915]] *ERROR* HWS Page address = 0x00000000
> [   64.368681] [drm:gen8_init_common_ring [i915]] *ERROR* HWS Page address = 0x00000000
> [   64.368704] [drm:gen8_init_common_ring [i915]] *ERROR* HWS Page address = 0x00000000
> 
> This patch reloads this value into the register during ring init.
> 
> Change-Id: Ibdd1e4645921b4deb02dfc8d0d8e6ba993ce7371
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0413b8f..73033f5 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1085,6 +1085,12 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring)
>  	I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
>  	I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
>  
> +	if (ring->status_page.obj) {
> +		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
> +			   (u32)ring->status_page.gfx_addr);
> +		POSTING_READ(RING_HWS_PGA(ring->mmio_base));
> +	}

I was going to suggest removing the same thing from the
lrc_setup_hardware_status_page(), but after another look it seems we
sometimes call .init_hw() before the context setup. Would be nice to
have a more consistent sequence for init and reset. But anyway the patch
looks OK to me. I verified that we indeed lose this register on GPU
reset.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> +
>  	I915_WRITE(RING_MODE_GEN7(ring),
>  		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
>  		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> -- 
> 2.3.0
> 
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-- 
Ville Syrjälä
Intel OTC