[Intel-gfx] [PATCH] drm/i915: Correcting the reg definitions for PORT_DFT

[Minu Mathai]

From: Minu <minu.mathai at intel.com>

Display CRCs were not readable because the register defintions
for PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
MMIO offset needs to be added to these register offsets to fix them.

Issue: GMINL-6869
Signed-off-by: Minu Mathai <minu.mathai at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7213224..c327c7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3193,7 +3193,7 @@ enum skl_disp_power_wells {
 #define PCH_HDMIC	0xe1150
 #define PCH_HDMID	0xe1160
 
-#define PORT_DFT_I9XX				0x61150
+#define PORT_DFT_I9XX				(dev_priv->info.display_mmio_offset + 0x61150)
 #define   DC_BALANCE_RESET			(1 << 25)
 #define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
-- 
1.9.1

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