[Intel-gfx] [PATCH] drm/i915: Correcting the reg definitions for PORT_DFT

[Ville Syrjälä]

On Tue, Jun 09, 2015 at 12:06:36PM +0000, Mathai, Minu wrote:
> The hardware composer test which found the problem with this register definition is used in Android testing and isn't open source. 
> However fixing this register definition will stop potential problems for  future use cases and would reduce the rebase effort for our Android tree.

What are you testing with this register? The register isn't even listed
in any VLV/CHV documentation so I have no idea what you would even do
with it.

> 
> -----Original Message-----
> From: Jani Nikula [mailto:jani.nikula at linux.intel.com] 
> Sent: Monday, June 8, 2015 2:48 PM
> To: Mathai, Minu; Ville Syrjälä
> Cc: intel-gfx at lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Correcting the reg definitions for PORT_DFT
> 
> On Mon, 08 Jun 2015, "Mathai, Minu" <minu.mathai at intel.com> wrote:
> > This change is needed for some hardware composer tests in chv.
> 
> As Ville said, this #define is not used by the upstream kernel on byt/chv. Maybe you have some out-of-tree patches using that?
> 
> BR,
> Jani.
> 
> 
> >
> > -----Original Message-----
> > From: Ville Syrjälä [mailto:ville.syrjala at linux.intel.com]
> > Sent: Friday, June 5, 2015 2:08 PM
> > To: Mathai, Minu
> > Cc: intel-gfx at lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Correcting the reg 
> > definitions for PORT_DFT
> >
> > On Fri, Jun 05, 2015 at 02:00:24PM +0100, Minu Mathai wrote:
> >> From: Minu <minu.mathai at intel.com>
> >> 
> >> Display CRCs were not readable because the register defintions for 
> >> PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
> >> MMIO offset needs to be added to these register offsets to fix them.
> >> 
> >> Issue: GMINL-6869
> >> Signed-off-by: Minu Mathai <minu.mathai at intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >> b/drivers/gpu/drm/i915/i915_reg.h index 7213224..c327c7c 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -3193,7 +3193,7 @@ enum skl_disp_power_wells {
> >>  #define PCH_HDMIC	0xe1150
> >>  #define PCH_HDMID	0xe1160
> >>  
> >> -#define PORT_DFT_I9XX				0x61150
> >> +#define PORT_DFT_I9XX				(dev_priv->info.display_mmio_offset + 0x61150)
> >
> > PORT_DFT_I9XX isn't used on VLV/CHV, so this doesn't change anything.
> >
> >
> >>  #define   DC_BALANCE_RESET			(1 << 25)
> >>  #define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
> >>  #define   DC_BALANCE_RESET_VLV			(1 << 31)
> >> --
> >> 1.9.1
> >> 
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> >
> > --
> > Ville Syrjälä
> > Intel OTC
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> 
> --
> Jani Nikula, Intel Open Source Technology Center

-- 
Ville Syrjälä
Intel OTC