[Intel-gfx] [PATCH v3 2/6] drm/i915/gen8: Re-order init pipe_control in lrc mode

[Dave Gordon]

On 05/06/15 11:34, Arun Siluvery wrote:
> Some of the WA applied using WA batch buffers perform writes to scratch page.
> In the current flow WA are initialized before scratch obj is allocated.
> This patch reorders intel_init_pipe_control() to have a valid scratch obj
> before we initialize WA.
> 
> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0b3422a..20c56e4 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1562,11 +1562,16 @@ static int logical_render_ring_init(struct drm_device *dev)
>  	ring->emit_bb_start = gen8_emit_bb_start;
>  
>  	ring->dev = dev;
> +
> +	ret = intel_init_pipe_control(ring);
> +	if (ret)
> +		return ret;
> +
>  	ret = logical_ring_init(dev, ring);
>  	if (ret)
>  		return ret;
>  
> -	return intel_init_pipe_control(ring);
> +	return 0;
>  }

You could squash the last several lines down to just:

	return logical_ring_init(dev, ring);

.Dave.