[Intel-gfx] [PATCH 1/2] drm/i915/bxt: work around HW coherency issue when accessing GPU seqno

[Chris Wilson]

On Thu, Jun 11, 2015 at 09:02:44AM +0100, Dave Gordon wrote:
> On 10/06/15 16:52, Chris Wilson wrote:
> > I seem to recall that we tried clflushing for gen6+, but we didn't
> > record any details, so it may be worth retesting ivb with that w/a.
> 
> Is that clflush on the CPU, or MI_CLFLUSH on the GPU? Does the latter
> help at all?

Only CPU. The w/a is required for all rings, and the MI_CFLUSH is RCS
only.

Anyway so far using clflush for gen6/ivb/hsw I haven't yet triggered the
failures, but there is a measurably improvement over the I915_READ().
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre