[Intel-gfx] [PATCH 1/3] drm/i915: Actually respect DSPSURF alignment restrictions

[Chris Wilson]

On Thu, Jun 11, 2015 at 04:31:14PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Currently intel_gen4_compute_page_offset() simply picks the closest
> page boundary below the linear offset. That however may not be suitably
> aligned to satisfy any hardware specific restrictions. So let's make
> sure the page boundary we choose is properly aligned.
> 
> Also to play it a bit safer lets split the remaining linear offset into
> x and y values instead of just x. This should make no difference for
> most platforms since we convert the x and y offsets back into a linear
> offset before feeding them to the hardware. HSW+ are different however
> and use x and y offsets even with linear buffers, so they might have
> trouble if either the x or y get too big.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---

> @@ -2455,12 +2461,13 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
>  
>  		return tile_rows * pitch * 8 + tiles * 4096;
>  	} else {
> +		unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
>  		unsigned int offset;
>  
>  		offset = *y * pitch + *x * cpp;
> -		*y = 0;
> -		*x = (offset & 4095) / cpp;
> -		return offset & -4096;
> +		*y = (offset & alignment) / pitch;
> +		*x = ((offset & alignment) - *y * pitch) / cpp;
> +		return offset & ~alignment;

Calculation looks solid. I presume we have a igt/kms test that combines
linear/tiled, large surfaces and large offsets?

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre