[Intel-gfx] [PATCH v2] drm/i915/skl: Retrieve the Rpe value from Pcode

[Ville Syrjälä]

On Fri, Jun 12, 2015 at 03:01:08PM +0530, akash.goel at intel.com wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> Read the efficient frequency (aka RPe) value through the the mailbox
> command (0x1A) from the pcode, as done on Haswell and Broadwell.
> The turbo minimum frequency softlimit is not revised as per the
> efficient frequency value.
> 
> v2: Replaced the conditional expression operator with 'if' statement (Tom)
> 
> Issue: VIZ-5143
> Signed-off-by: Akash Goel <akash.goel at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d091fec..21b22a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4314,16 +4314,20 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
>  	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
>  
>  	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
> -	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
>  		ret = sandybridge_pcode_read(dev_priv,
>  					HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
>  					&ddcc_status);
> -		if (0 == ret)
> +		if (0 == ret) {
>  			dev_priv->rps.efficient_freq =
>  				clamp_t(u8,
>  					((ddcc_status >> 8) & 0xff),
>  					dev_priv->rps.min_freq,
>  					dev_priv->rps.max_freq);

That's wrong now since min/max_freq were already multiplied by
GEN9_FREQ_SCALER.

> +
> +			if (IS_SKYLAKE(dev))
> +			      dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
> +		}
>  	}

I would suggest moving all the GEN9_FREQ_SCALER multiplications here.

>  
>  	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
> -- 
> 1.9.2
> 
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-- 
Ville Syrjälä
Intel OTC