[Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+

[Chris Wilson]

On Thu, Jun 11, 2015 at 04:02:27PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> This commit is just to make the intentions explicit: on HSW+ these
> bits are MBZ, but since we only support plane A and the macro
> evaluates to zero when plane A is the parameter, we're not fixing any
> bug.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 9b300bd..8b980e5 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -258,11 +258,14 @@ static void gen7_fbc_enable(struct drm_crtc *crtc)
>  	struct drm_framebuffer *fb = crtc->primary->fb;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	u32 dpfc_ctl;
> +	u32 dpfc_ctl = 0;
>  
>  	dev_priv->fbc.enabled = true;
>  
> -	dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
> +
An extra line of whitespace, just because.

Minor bikeshed would be to dpfc_ctl = 0 here, so that the construction
of dpfc_ctl is in a single logical block (admittedly in this case you
have have to read back a few lines to find the initializer).

> +	if (IS_IVYBRIDGE(dev))
> +		dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane);
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre