[Intel-gfx] [PATCH 1/3] drm/i915: Fix command parser to validate multiple register access with the same command.

[Ville Syrjälä]

On Mon, Jun 15, 2015 at 02:18:01PM +0300, Francisco Jerez wrote:
> Daniel Vetter <daniel at ffwll.ch> writes:
> 
> > On Tue, Jun 02, 2015 at 05:36:26PM +0800, Zhigang Gong wrote:
> >> The patchset LGTM and works well with beignet. The 80%+ performance regression issue in darktable also has been fixed
> >> after this patchset applied and enable the atomic in L3 at beignet side. So,
> >> 
> >> Reviewed-by: Zhigang Gong <zhigang.gong at linux.intel.com>
> >
> > All three merged.
> 
> Thanks Daniel.
> 
> > Aside: Dont we need an increment for the cmd parser version for
> > userspace to be able to detect this?
> >
> Yeah, that would be a good idea, patch attached.

The old version alloweed userspace to write basically any register, the
new version allows only the whitelisted registers. I don't see how a
version number bump would help anyone.

> 
> > And please follow up with a link to the beignet patches used to validate
> > these kernel patches for references.
> >
> Zhigang, do you have a link to your Beignet patch?
> 
> > Thanks, Daniel
> >
> >> 
> >> Thanks,
> >> Zhigang Gong.
> >> 

> From 9f26beaf96473800252db35c4513933ae43e3c84 Mon Sep 17 00:00:00 2001
> From: Francisco Jerez <currojerez at riseup.net>
> Date: Mon, 15 Jun 2015 14:03:29 +0300
> Subject: [PATCH] drm/i915: Bump command parser version number.
> 
> Signed-off-by: Francisco Jerez <currojerez at riseup.net>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 0146fe6..6722098 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1219,6 +1219,7 @@ int i915_cmd_parser_get_version(void)
>  	 * 2. Allow access to the MI_PREDICATE_SRC0 and
>  	 *    MI_PREDICATE_SRC1 registers.
>  	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> +	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
>  	 */
> -	return 3;
> +	return 4;
>  }
> -- 
> 2.4.3
> 




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-- 
Ville Syrjälä
Intel OTC