[Intel-gfx] [PATCH v3] drm/i915: Limit CHV max cdclk

[Jani Nikula]

On Fri, 12 Jun 2015, Mika Kahola <mika.kahola at intel.com> wrote:
> Limit CHV maximum cdclk to 320MHz.
>
> v2: Rebase to the latest
> v3: Clean up of if-else tree
>
> Signed-off-by: Mika Kahola <mika.kahola at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

http://mid.gmane.org/20150415191900.GM1237@intel.com


> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5cc2263..c027012 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5256,6 +5256,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  			dev_priv->max_cdclk_freq = 540000;
>  		else
>  			dev_priv->max_cdclk_freq = 675000;
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		dev_priv->max_cdclk_freq = 320000;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->max_cdclk_freq = 400000;
>  	} else {
> -- 
> 1.9.1
>
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-- 
Jani Nikula, Intel Open Source Technology Center