[Intel-gfx] [PATCH 13/15] drm/i915: Integrate GuC-based command submission

[Chris Wilson]

On Mon, Jun 15, 2015 at 07:36:31PM +0100, Dave Gordon wrote:
> From: Alex Dai <yu.dai at intel.com>
> 
> GuC-based submission is mostly the same as execlist mode, up to
> intel_logical_ring_advance_and_submit(), where the context being
> dispatched would be added to the execlist queue; at this point
> we submit the context to the GuC backend instead.
> 
> There are, however, a few other changes also required, notably:
> 1.  Contexts must be pinned at GGTT addresses accessible by the GuC
>     i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
>     PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
> 
> 2.  The GuC's TLB must be invalidated after a context is pinned at
>     a new GGTT address.
> 
> 3.  GuC firmware uses the one page before Ring Context as shared data.
>     Therefore, whenever driver wants to get base address of LRC, we
>     will offset one page for it. LRC_PPHWSP_PN is defined as the page
>     number of LRCA.
> 
> 4.  In the work queue used to pass requests to the GuC, the GuC
>     firmware requires the ring-tail-offset to be represented as an
>     11-bit value, expressed in QWords. Therefore, the ringbuffer
>     size must be reduced to the representable range (4 pages).

I don't like how this sabotages the existing execlists implementation
in order for i915_guc_submission (an interesting choice of file name,
since we go i915_gem_execbuffer (API) -> intel_execlists (HW) ->
i915_guc_submission (HW), not fitting into our, admittedly loose, naming
convention very well) to share a few functions. Even a couple of which
are already vfunc.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre