[Intel-gfx] [PATCH 1/1] drm/i915: Tracepoints for profiling DC9 entry and exit programming

[Sagar Arun Kamble]

DC9 entry and exit programming is critical part of suspend/resume
sequences. This patch adds tracepoints that can help analyze time
taken using analyze_suspend.py/FTrace.

Change-Id: I22fca5313c4349f8937eeb5a1c441c8ef76e5f4e
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 78ef0bb..6797650 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -39,6 +39,7 @@
 #include <linux/module.h>
 #include <linux/pm_runtime.h>
 #include <drm/drm_crtc_helper.h>
+#include <trace/events/power.h>
 
 static struct drm_driver driver;
 
@@ -1061,12 +1062,16 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
 
+	trace_suspend_resume(TPS("dc_state_entry"), DC9_STATE, true);
+
 	/* TODO: when DC5 support is added disable DC5 here. */
 
 	broxton_ddi_phy_uninit(dev);
 	broxton_uninit_cdclk(dev);
 	bxt_enable_dc9(dev_priv);
 
+	trace_suspend_resume(TPS("dc_state_entry"), DC9_STATE, false);
+
 	return 0;
 }
 
@@ -1076,6 +1081,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
 
 	/* TODO: when CSR FW support is added make sure the FW is loaded */
 
+	trace_suspend_resume(TPS("dc_state_exit"), DC9_STATE, true);
+
 	bxt_disable_dc9(dev_priv);
 
 	/*
@@ -1086,6 +1093,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
 	broxton_ddi_phy_init(dev);
 	intel_prepare_ddi(dev);
 
+	trace_suspend_resume(TPS("dc_state_exit"), DC9_STATE, false);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b979ad..cf83ec8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7290,6 +7290,7 @@ enum skl_disp_power_wells {
 #define  DC_STATE_EN_DC9		(1<<3)
 #define  DC_STATE_EN_UPTO_DC6		(2<<0)
 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
+#define  DC9_STATE			9
 
 #define  DC_STATE_DEBUG                  0x45520
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1<<1)
-- 
1.9.1