[Intel-gfx] [PATCH 1/2] drm/i915: factor out intel_mode_target_cdclk

[Imre Deak]

For GEN9 the target cdclk frequency is needed during the modeset state check
phase too, so factor out this functionality.

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++++--------------
 1 file changed, 30 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2641053..9b68a5c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5899,21 +5899,37 @@ static int intel_mode_max_pixclk(struct drm_device *dev,
 	return max_pixclk;
 }
 
-static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
+static int intel_mode_target_cdclk(struct drm_i915_private *dev_priv,
+				   struct drm_atomic_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->dev);
-	struct drm_crtc *crtc;
-	struct drm_crtc_state *crtc_state;
-	int max_pixclk = intel_mode_max_pixclk(state->dev, state);
-	int cdclk, ret = 0;
+	int max_pixclk = intel_mode_max_pixclk(dev_priv->dev, state);
+	int cdclk;
 
 	if (max_pixclk < 0)
 		return max_pixclk;
 
-	if (IS_VALLEYVIEW(dev_priv))
-		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
-	else
+	if (IS_BROXTON(dev_priv)) {
 		cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
+	} else if (IS_VALLEYVIEW(dev_priv)) {
+		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+	} else {
+		MISSING_CASE(INTEL_INFO(dev_priv));
+		cdclk = 0;
+	}
+
+	return cdclk;
+}
+
+static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *crtc_state;
+	int cdclk, ret = 0;
+
+	cdclk = intel_mode_target_cdclk(dev_priv, state);
+	if (cdclk < 0)
+		return cdclk;
 
 	if (cdclk == dev_priv->cdclk_freq)
 		return 0;
@@ -5981,16 +5997,14 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *old_sta
 {
 	struct drm_device *dev = old_state->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int max_pixclk = intel_mode_max_pixclk(dev, NULL);
 	int req_cdclk;
 
-	/* The path in intel_mode_max_pixclk() with a NULL atomic state should
+	/* The path in intel_mode_target_cdclk() with a NULL atomic state should
 	 * never fail. */
-	if (WARN_ON(max_pixclk < 0))
+	req_cdclk = intel_mode_target_cdclk(dev_priv, NULL);
+	if (WARN_ON(req_cdclk < 0))
 		return;
 
-	req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
-
 	if (req_cdclk != dev_priv->cdclk_freq) {
 		/*
 		 * FIXME: We can end up here with all power domains off, yet
@@ -9556,15 +9570,13 @@ static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
 {
 	struct drm_device *dev = old_state->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int max_pixclk = intel_mode_max_pixclk(dev, NULL);
 	int req_cdclk;
 
 	/* see the comment in valleyview_modeset_global_resources */
-	if (WARN_ON(max_pixclk < 0))
+	req_cdclk = intel_mode_target_cdclk(dev_priv, NULL);
+	if (WARN_ON(req_cdclk < 0))
 		return;
 
-	req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
-
 	if (req_cdclk != dev_priv->cdclk_freq)
 		broxton_set_cdclk(dev, req_cdclk);
 }
-- 
2.1.4