[Intel-gfx] [PATCH 1/3] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

[Paulo Zanoni]

2015-02-13 17:37 GMT-02:00 Damien Lespiau <damien.lespiau at intel.com>:
> While we only need to restore pipe B/C interrupt registers on BDW when
> enabling the power well, skylake a bit more flexible and we'll also need
> to restore the pipe A registers as it has its own power well that can be
> toggled.

- I'll admit I had to open the gcc operator precedence table to check
for those "a & b << c" without parens :)
- Reading "PIPE_C | PIPE_B" increases my anxiety levels.
- Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c         | 15 ++++++++++-----
>  drivers/gpu/drm/i915/intel_drv.h        |  3 ++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 ++-
>  3 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e71d2b2..65fe9e7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3229,15 +3229,20 @@ static void gen8_irq_reset(struct drm_device *dev)
>         ibx_irq_reset(dev);
>  }
>
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
> +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> +                                    unsigned int pipe_mask)
>  {
>         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>
>         spin_lock_irq(&dev_priv->irq_lock);
> -       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
> -                         ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
> -       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
> -                         ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
> +       if (pipe_mask & 1 << PIPE_B)
> +               GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
> +                                 dev_priv->de_irq_mask[PIPE_B],
> +                                 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
> +       if (pipe_mask & 1 << PIPE_C)
> +               GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
> +                                 dev_priv->de_irq_mask[PIPE_C],
> +                                 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
>         spin_unlock_irq(&dev_priv->irq_lock);
>  }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1de8e20..f9a96bd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -818,7 +818,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
>  }
>
>  int intel_get_crtc_scanline(struct intel_crtc *crtc);
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
> +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> +                                    unsigned int pipe_mask);
>
>  /* intel_crt.c */
>  void intel_crt_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6d8e29a..35e0cb6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
>         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
>
>         if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
> -               gen8_irq_power_well_post_enable(dev_priv);
> +               gen8_irq_power_well_post_enable(dev_priv,
> +                                               1 << PIPE_C | 1 << PIPE_B);
>  }
>
>  static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> --
> 1.8.3.1
>
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-- 
Paulo Zanoni