[Intel-gfx] Intel-gfx Digest, Vol 85, Issue 280

[Arun R Murthy]

> -----------------------------
>
> Message: 2
> Date: Thu, 26 Feb 2015 21:01:04 +0200
> From: ville.syrjala at linux.intel.com
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 12/12] drm/i915: Enable the maxfifo PM5
> 	mode	when appropriate on CHV
> Message-ID:
> 	<1424977264-24764-1-git-send-email-ville.syrjala at linux.intel.com>
> Content-Type: text/plain; charset=UTF-8
>
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> CHV has a new knob in Punit to select between some memory power savings modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is enabled, so let's do so in the hopes for moar power savings.
>
> v2: Put the thing into a separate function to avoid churn later
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  3 +++  drivers/gpu/drm/i915/intel_pm.c | 19 ++++++++++++++++++-
>   2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 145f0d4..5a20f58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -552,6 +552,9 @@
>   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>   #define   DSPFREQGUAR_SHIFT			14
>   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
>   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
>   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
>   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e6cbc24..f603dac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -235,13 +235,30 @@ static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
>   	return NULL;
>   }
>   
> +static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool
> +enable) {
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +	if (enable)
> +		val |= DSP_MAXFIFO_PM5_ENABLE;
> +	else
> +		val &= ~DSP_MAXFIFO_PM5_ENABLE;
> +	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> +
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +}
> +
>   void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)  {
>   	struct drm_device *dev = dev_priv->dev;
>   	u32 val;
>   
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
>   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +		chv_set_memory_pm5(dev_priv, enable);
>   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
>   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
>   	} else if (IS_PINEVIEW(dev)) {
> --
> 2.0.5
Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>

Thanks and Regards,
Arun R Murthy
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