[Intel-gfx] [PATCH] drm/i915: Changes for calculating dsi clk for CHT

[shuang.he at intel.com]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
Task id: 5875
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -5              278/278              273/278
ILK                                  308/308              308/308
SNB                 -1              284/284              283/284
IVB                                  380/380              380/380
BYT                                  294/294              294/294
HSW                 -1              387/387              386/387
BDW                 -1              316/316              315/316
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-sync      NO_RESULT(1)CRASH(5)NRUN(1)PASS(7)      CRASH(1)PASS(1)
 PNV  igt_gem_userptr_blits_coherency-unsync      NO_RESULT(1)CRASH(4)PASS(6)      CRASH(2)
 PNV  igt_gen3_render_linear_blits      FAIL(4)NRUN(1)DMESG_WARN(1)PASS(7)      FAIL(2)
 PNV  igt_gen3_render_mixed_blits      FAIL(7)PASS(9)      FAIL(2)
 PNV  igt_gem_fence_thrash_bo-write-verify-threaded-none      FAIL(2)CRASH(4)PASS(4)      FAIL(1)CRASH(1)
*SNB  igt_gem_fence_thrash_bo-write-verify-x      PASS(2)      DMESG_WARN(1)PASS(1)
*HSW  igt_gem_storedw_loop_vebox      PASS(2)      DMESG_WARN(2)
*BDW  igt_gem_gtt_hog      PASS(18)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'