[Intel-gfx] [PATCH 12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV

[Purushothaman, Vijay A]

On 2/10/2015 6:58 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> CHV has a new knob in Punit to select between some memory power savings
> modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
> enabled, so let's do so in the hopes for moar power savings.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
>   2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0a7688..2196e57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -552,6 +552,9 @@
>   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>   #define   DSPFREQGUAR_SHIFT			14
>   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
>   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
>   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
>   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e6cbc24..4e11552 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>   	struct drm_device *dev = dev_priv->dev;
>   	u32 val;
>   
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +		if (enable)
> +			val |= DSP_MAXFIFO_PM5_ENABLE;
> +		else
> +			val &= ~DSP_MAXFIFO_PM5_ENABLE;
> +		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (IS_VALLEYVIEW(dev)) {
>   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
>   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Since you are enabling MaxFIFO for multi plane in one of the previous 
patches, i guess PM5 will also be enabled when more than one plane is 
active in this flow.
Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
is the only validated scenario by SV.

With this addressed,
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman at linux.intel.com>

Thanks,
Vijay