[Intel-gfx] [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV

[Daniel Vetter]

On Thu, Mar 05, 2015 at 09:19:48PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Poke at the CBR1_VLV register during init_clock_gating to make sure the
> PND deadline scheme is used.
> 
> The hardware has two modes of operation wrt. watermarks:
> 
> 1) PND deadline mode:
>  - memory request deadline is calculated from actual FIFO level * DDL
>  - WM1 watermark values are unused (AFAIK)
>  - WM watermark level defines when to start fetching data from memory
>    (assuming trickle feed is not used)
> 
> 2) backup mode
>  - deadline is based on FIFO status, DDL is unused
>  - FIFO split into three regions with WM and WM1 watermarks, each
>    part specifying a different FIFO status
> 
> We want to use the PND deadline mode, so let's make sure the chicken
> bit is in the correct position on init.
> 
> Also take the opportunity to refactor the shared code between VLV and
> CHV to a shared function.
> 
> Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Merged up to this one (had to resolve some minor conflicts with the
ongoing stateification work from Matt).

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------
>  2 files changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b48f4b..8178610 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells {
>  #define DDL_PRECISION_LOW		(0<<7)
>  #define DRAIN_LATENCY_MASK		0x7f
>  
> +#define CBR1_VLV			(VLV_DISPLAY_BASE + 0x70400)
> +#define  CBR_PND_DEADLINE_DISABLE	(1<<31)
> +
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE	64
>  #define I915_FIFO_LINE_SIZE	64
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 27ce40c..bdb0f5d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	gen6_check_mch_setup(dev);
>  }
>  
> +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +
> +	/*
> +	 * Disable trickle feed and enable pnd deadline calculation
> +	 */
> +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	I915_WRITE(CBR1_VLV, 0);
> +}
> +
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +	vlv_init_display_clock_gating(dev_priv);
>  
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
> @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_UCGCTL4,
>  		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>  
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> -
>  	/*
>  	 * BSpec says this must be set, even though
>  	 * WaDisable4x2SubspanOptimization isn't listed for VLV.
> @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	vlv_init_display_clock_gating(dev_priv);
>  
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
> -- 
> 2.0.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch