[Intel-gfx] [PATCH 2/2] drm/i915: Fix chv cdclk support

[Purushothaman, Vijay A]

On 3/2/2015 11:37 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The specs seem to be full of misinformation wrt. the Punit register
> 0x36. Some versions still show the old VLV bit layout, some the new
> layout, and all of them seem to tell us nonsense about the cdclk
> value encoding.
>
> Testing on actual hardware has shown that we simply need to program
> the desired CCK divider into the Punit register using the new layout of
> the bits. Doing that, the status bit change to indicate the same value,
> and the CCK 0x6b register also changes accordingly to indicate that CCK
> is now using the new divider.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman at linux.intel.com>

Thanks,
Vijay


> ---
>   drivers/gpu/drm/i915/intel_display.c | 23 +++++++----------------
>   1 file changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 94ff310..ca49b6f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4889,24 +4889,23 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>   	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
>   
>   	switch (cdclk) {
> -	case 400000:
> -		cmd = 3;
> -		break;
>   	case 333333:
>   	case 320000:
> -		cmd = 2;
> -		break;
>   	case 266667:
> -		cmd = 1;
> -		break;
>   	case 200000:
> -		cmd = 0;
>   		break;
>   	default:
>   		MISSING_CASE(cdclk);
>   		return;
>   	}
>   
> +	/*
> +	 * Specs are full of misinformation, but testing on actual
> +	 * hardware has shown that we just need to write the desired
> +	 * CCK divider into the Punit register.
> +	 */
> +	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
> +
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
>   	val &= ~DSPFREQGUAR_MASK_CHV;
> @@ -4928,10 +4927,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>   	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
>   	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
>   
> -	/* FIXME: Punit isn't quite ready yet */
> -	if (IS_CHERRYVIEW(dev_priv->dev))
> -		return 400000;
> -
>   	/*
>   	 * Really only a few cases to deal with, as only 4 CDclks are supported:
>   	 *   200MHz
> @@ -5606,10 +5601,6 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
>   	u32 val;
>   	int divider;
>   
> -	/* FIXME: Punit isn't quite ready yet */
> -	if (IS_CHERRYVIEW(dev))
> -		return 400000;
> -
>   	if (dev_priv->hpll_freq == 0)
>   		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
>