[Intel-gfx] [PATCH 00/13] drm/i915: Clean up the DP link rate code

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

We have a bit of a mess with the source vs. sink link rate handling, so I
went ahead and tried to clean it up. So now we keep the source and sink
rates neatly in their own corners and compute the intersection when needed.

I considered storing the intersection itself under intel_dp, but for
eDP 1.4 we need to convert the chose rate back to the index from which
we got, which means keeping the original sink rates around as well. So
in the end I figured it's not a huge deal if we keep computing the
intersection on demand.

I also ended up adding eDP 1.4 intermediate frequency support for CHV, but
as I don't have an eDP 1.4 panel in my BSW I couldn't actually test it.

Ville Syrjälä (13):
  drm/i915: Make the DP rates int instead of uint32_t
  drm/i915: Store the converted link rates in
    intel_dp->supported_rates[]
  drm/i915: Don't copy the DP source rates arrays
  drm/i915: Don't copy sink rates either
  drm/i915: Remove special case from intel_supported_rates()
  drm/i915: Fully separate source vs. sink rates
  drm/i915: Hide the source vs. sink rate handling from
    intel_dp_compute_config()
  drm/i915: Fix max link rate in intel_dp_mode_valid()
  drm/i915: Use DP_LINK_RATE_SET whenever possible
  drm/i915: Fix MST link rate handling
  drm/i915: Avoid overflowing the DP link rate arrays
  drm/i915: Add eDP intermediate frequencies for CHV
  drm/i915: Include the sink/source/supported rates in debug output

 drivers/gpu/drm/i915/intel_dp.c     | 221 +++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp_mst.c |  16 ++-
 drivers/gpu/drm/i915/intel_drv.h    |   6 +-
 3 files changed, 157 insertions(+), 86 deletions(-)

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2.0.5