[Intel-gfx] [PATCH 07/21] drm/i915: Helper function to update skylake scaling ratio.

[Chandra Konduru]

Helper function updates supported scaling ratios based on cdclk and
crtc clocks.

Signed-off-by: Chandra Konduru <chandra.konduru at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index da78e77..5591282 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4511,6 +4511,31 @@ static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
 	intel_wait_for_vblank(dev, other_active_crtc->pipe);
 }
 
+static void skl_update_scaling_ratio(struct drm_device *dev,
+	struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t crtc_clock, cdclk;
+	int i;
+
+	if (INTEL_INFO(dev)->gen < 9 || !crtc_state)
+		return;
+
+	crtc_clock = (uint32_t) crtc_state->base.adjusted_mode.crtc_clock;
+	cdclk = (uint32_t) intel_ddi_get_cdclk_freq(dev_priv);
+
+	if (!crtc_clock || !cdclk)
+		return;
+
+	for (i = 0; i < crtc_state->scaler_state.num_scalers; i++) {
+		struct intel_scaler *scaler = &crtc_state->scaler_state.scalers[i];
+
+		scaler->min_hsr = max(scaler->min_hsr, (crtc_clock * 100)/cdclk);
+		scaler->min_vsr = max(scaler->min_hsr, (crtc_clock * 100)/cdclk);
+		scaler->min_hvsr = max(scaler->min_hsr, (crtc_clock * 100)/cdclk);
+	}
+}
+
 static void haswell_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
-- 
1.7.9.5