[Intel-gfx] [PATCH 30/49] drm/i915/bxt: add display initialize/uninitialize sequence

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b91862e..ba2d1ae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8284,6 +8284,75 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  	intel_prepare_ddi(dev);
>  }
>  
> +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
> +				int max_pixclk)
> +{
> +	/*
> +	 * CDclks are supported:
> +	 *   144MHz
> +	 *   288MHz
> +	 *   384MHz
> +	 *   576MHz
> +	 *   624MHz
> +	 * Check to see whether we're above 90% of the lower bin and
> +	 * adjust if needed.
> +	 */
> +
> +	/* If max_pixclk is greater than the max allowed clock, return 0.
> +	 * FIXME:- The max clock allowed needs to be provided by GOP/VBIOS
> +	 * via a scratch pad register. Till that is enabled, use 624MHz as max.
> +	 */
> +	if (max_pixclk > 624000)
> +		return 0;
> +	else if (max_pixclk > 576000*9/10)
> +		return 624000;
> +	else if (max_pixclk > 384000*9/10)
> +		return 576000;
> +	else if (max_pixclk > 288000*9/10)
> +		return 384000;
> +	else if (max_pixclk > 144000*9/10)

Does BXT really need a 10% guarband for CDCLK? Other HSW+ platforms need no
guardband IIRC (assuming we ignore 64bpp and scaling).

I'm not seeing anything specific about BXT max pixel rate in BSpec.
The SKL section says EXCLUDE(BXT). Art, can you clarify?

> +		return 288000;
> +	else
> +		return 144000;
> +}
> +

-- 
Ville Syrjälä
Intel OTC