[Intel-gfx] [PATCH 43/49] drm/i915/bxt: Determine PLL attached to pipe

[Jesse Barnes]

On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m at intel.com>
> 
> Determine PLL attached to pipe (which is same as DDI PLL)
> 
> v2:
> - rebased on upstream s/crtc_config/crtc_state/ (imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m at intel.com> (v1)
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 411bf50..c060496 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8468,6 +8468,28 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  	return 0;
>  }
>  
> +static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> +				enum port port,
> +				struct intel_crtc_state *pipe_config)
> +{
> +	switch (port) {
> +	case PORT_A:
> +		pipe_config->ddi_pll_sel = SKL_DPLL0;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
> +		break;
> +	case PORT_B:
> +		pipe_config->ddi_pll_sel = SKL_DPLL1;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
> +		break;
> +	case PORT_C:
> +		pipe_config->ddi_pll_sel = SKL_DPLL2;
> +		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
> +		break;
> +	default:
> +		DRM_ERROR("Incorrect port type\n");
> +	}
> +}
> +
>  static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
> @@ -8530,6 +8552,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  
>  	if (IS_SKYLAKE(dev))
>  		skylake_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (IS_BROXTON(dev))
> +		bxt_get_ddi_pll(dev_priv, port, pipe_config);
>  	else
>  		haswell_get_ddi_pll(dev_priv, port, pipe_config);
>  
> 

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>