[Intel-gfx] [PATCH 14/49] drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround

[Nick Hoath]

On 17/03/2015 13:06, Imre Deak wrote:
> On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
>> On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
>>> Signed-off-by: Imre Deak <imre.deak at intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>   1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 3d4a7c3..d5dd0b3 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev)
>>>
>>>   static void bxt_init_clock_gating(struct drm_device *dev)
>>>   {
>>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>>   	gen9_init_clock_gating(dev);
>>> +
>>> +	/*
>>> +	 * FIXME:
>>> +	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
>>
>> We have pci revid macros now. Do you have plans to roll similar ones out
>> for bxt?
>
> Yes. It may be that for BXT we also need to look at the PCI_REVISION_ID
> field besides PCI_CLASS_REVISION, I still have to figure out the exact
> mapping. (And also understand the meaning/difference between SOC vs. GT
> revision IDs).

I've posted a patch with the Broxton revision ID's from the specs.

>
> --Imre
>
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