[Intel-gfx] [PATCH] drm/i915: Add fault address to error state for gen8 and gen9

[Ville Syrjälä]

On Tue, Mar 24, 2015 at 02:06:57PM +0200, Mika Kuoppala wrote:
> The faulting virtual address is >32bits and has been moved
> to different registers. Add to error state and output upper
> register first, in the same line for easy reconstruction of
> the fault address.
> 
> v2: correct gen masking (Michel)
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 ++
>  drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++
>  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4dbe743..3ec70a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -427,6 +427,8 @@ struct drm_i915_error_state {
>  	u32 forcewake;
>  	u32 error; /* gen6+ */
>  	u32 err_int; /* gen7 */
> +	u32 fault_data0; /* gen8, gen9 */
> +	u32 fault_data1; /* gen8, gen9 */
>  	u32 done_reg;
>  	u32 gac_eco;
>  	u32 gam_ecochk;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f7cbd3..a538ee1 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -386,6 +386,11 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
>  		err_printf(m, "ERROR: 0x%08x\n", error->error);
> +
> +		if (INTEL_INFO(dev)->gen >= 8)
> +			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
> +				   error->fault_data1, error->fault_data0);
> +
>  		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
>  	}
>  
> @@ -1171,6 +1176,11 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  	if (IS_GEN7(dev))
>  		error->err_int = I915_READ(GEN7_ERR_INT);
>  
> +	if (INTEL_INFO(dev)->gen >= 8) {
> +		error->fault_data0 = I915_READ(GEN8_FAULT_TBL_DATA0);
> +		error->fault_data1 = I915_READ(GEN8_FAULT_TBL_DATA1);
> +	}
> +
>  	if (IS_GEN6(dev)) {
>  		error->forcewake = I915_READ(FORCEWAKE);
>  		error->gab_ctl = I915_READ(GAB_CTL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b84ee6..c663b3c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1306,6 +1306,9 @@ enum skl_disp_power_wells {
>  #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
>  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<(pipe*3))
>  
> +#define GEN8_FAULT_TBL_DATA0		0x04b10
> +#define GEN8_FAULT_TBL_DATA1		0x04b14

TLB

> +
>  #define FPGA_DBG		0x42300
>  #define   FPGA_DBG_RM_NOCLAIM	(1<<31)
>  
> -- 
> 1.9.1
> 
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-- 
Ville Syrjälä
Intel OTC