[Intel-gfx] [PATCH RFC] drm/i915: Pad GTT views of exec objects up to user specified size

[Tvrtko Ursulin]

On 03/25/2015 01:29 PM, Chris Wilson wrote:
> Our GPUs impose certain requirements upon buffers that depend upon how
> exactly they are used. Typically this is expressed as that they require
> a larger surface than would be naively computed by pitch * height.
> Normally such requirements are hidden away in the userspace driver, but
> when we accept pointers from strangers and later impose extra conditions
> on them, the original client allocator has no idea about the
> monstrosities in the GPU and we require the userspace driver to inform
> the kernel how many padding pages are required beyond the client
> allocation.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
> Tvrtko is working on an igt to exercise this feature. The original
> request basically stems from trying to mix client allocations (userptr)
> and tiling. But I see it as a nice extension of our lazy_fencing code to
> reduce buffer sizes for tiled allocations (as we then do not need to
> allocate the entire last tilerow) and for relaxing restrictions on
> foriegn buffers like DRI3.
> ---

(Original request was actually about sampler overfetch in various 
texture modes.)

We talked about per-process (or so) scratch pages before. I looked now 
but I see at the moment even PPGTT shares the same scratch page so 
presumably that means someone has thought about security and decided 
that is fine?

Otherwise looks good to me.

Regards,

Tvrtko