[Intel-gfx] [PATCH 33/49] drm/i915: Reduce locking in gen8 IRQ handler

[Chris Wilson]

On Fri, Mar 27, 2015 at 03:13:08PM +0100, Daniel Vetter wrote:
> On Fri, Mar 27, 2015 at 11:02:05AM +0000, Chris Wilson wrote:
> > Similar in vain in reducing the number of unrequired spinlocks used for
> > execlist command submission (where the forcewake is required but
> > manually controlled), we know that the IRQ registers are outside of the
> > powerwell and so we can access them directly. Since we now have direct
> > access exported via I915_READ_FW/I915_WRITE_FW, lets put those to use in
> > the irq handlers as well.
> > 
> > In the process, reorder the execlist submission to happen as early as
> > possible.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> port/pipe interrupts are in display power domains afaik, so I'd prefer not
> to lose pm debug with those. But they're also gated behind the master_ctl
> bits, so can we have all of the speedups still without touching those?

Sure, execlists triggers gen8_gt_irq_handler() a lot, so we can just
limit the use of raw reads/writes there. Probably safer in the long run
as well.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre