[Intel-gfx] [PATCH] drm/i915: PSR: Keep sink state consistent with source

[Vivi, Rodrigo]

Thanks

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

On Fri, 2015-03-27 at 17:21 +0530, Durgadoss R wrote:
> BSpec recommends to keep the main link state consistent
> between the source and the sink. As per that, update
> the main link state in sink DPCD register to 'active',
> for Valleyview based platforms.
> 
> Signed-off-by: Durgadoss R <durgadoss.r at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b9f40c2..94e14f2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -133,7 +133,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
>  static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>  {
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> -			   DP_PSR_ENABLE);
> +			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>  }
>  
>  static void hsw_psr_enable_sink(struct intel_dp *intel_dp)