[Intel-gfx] [PATCH 02.1/49] drm/i915: use proper FBC base register on all new platforms

[Antti Koskipää]

Reviewed-by: Antti Koskipää <antti.koskipaa at linux.intel.com>

On 03/26/2015 05:35 PM, Imre Deak wrote:
> Starting from GEN5 the FBC base register is the same on all platforms.
> GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make
> things work on BXT as well.
> 
> Motivated by Rodrigo's request to check FBC support on BXT.
> 
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f8da716..348ed5a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
>  
>  	dev_priv->fbc.threshold = ret;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (INTEL_INFO(dev_priv)->gen >= 5)
>  		I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
>  	else if (IS_GM45(dev)) {
>  		I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
>