[Intel-gfx] [PATCH 2/2] drm/i915/bxt: Add BXT HW status to SSEU status

[jeff.mcgee at intel.com]

From: Jeff McGee <jeff.mcgee at intel.com>

BXT uses the same power gate control ack message registers as
SKL. BXT makes use of additional fields which indicate the
power gating state of each subslice in BXT's single slice.

Signed-off-by: Jeff McGee <jeff.mcgee at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  3 +++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 007c7d7..6c5ba28 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4566,6 +4566,41 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 				eu_per = max(eu_per, eu_cnt);
 			}
 		}
+	} else if (IS_BROXTON(dev)) {
+		const int ss_max = 3;
+		int ss;
+		u32 s_reg, eu_reg[2], eu_mask[2];
+
+		s_reg = I915_READ(GEN9_SLICE0_PGCTL_ACK);
+		eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
+		eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
+		eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+			     GEN9_PGCTL_SSA_EU19_ACK |
+			     GEN9_PGCTL_SSA_EU210_ACK |
+			     GEN9_PGCTL_SSA_EU311_ACK;
+		eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+			     GEN9_PGCTL_SSB_EU19_ACK |
+			     GEN9_PGCTL_SSB_EU210_ACK |
+			     GEN9_PGCTL_SSB_EU311_ACK;
+
+		if (s_reg & GEN9_PGCTL_SLICE_ACK) {
+
+			s_tot = 1;
+			for (ss = 0; ss < ss_max; ss++) {
+				unsigned int eu_cnt;
+
+				if (!(s_reg & (GEN9_PGCTL_SS0_ACK << (2 * ss))))
+					/* skip disabled subslice */
+					continue;
+
+				ss_per++;
+				eu_cnt = 2 * hweight32(eu_reg[ss/2] &
+						       eu_mask[ss%2]);
+				eu_tot += eu_cnt;
+				eu_per = max(eu_per, eu_cnt);
+			}
+		}
+		ss_tot = ss_per;
 	}
 	seq_printf(m, "  Enabled Slice Total: %u\n", s_tot);
 	seq_printf(m, "  Enabled Subslice Total: %u\n", ss_tot);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e1a0fd9..be6554f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6275,6 +6275,9 @@ enum skl_disp_power_wells {
 #define GEN9_SLICE1_PGCTL_ACK		0x8050
 #define GEN9_SLICE2_PGCTL_ACK		0x8054
 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
+#define   GEN9_PGCTL_SS0_ACK		(1 << 2) /* Only for SLICE0 */
+#define   GEN9_PGCTL_SS1_ACK		(1 << 4) /* Only for SLICE0 */
+#define   GEN9_PGCTL_SS2_ACK		(1 << 6) /* Only for SLICE0 */
 
 #define GEN9_SLICE0_SS01_EU_PGCTL_ACK	0x805c
 #define GEN9_SLICE0_SS23_EU_PGCTL_ACK	0x8060
-- 
2.3.3