[Intel-gfx] [PATCH v3] drm/i915: Setup static bias for GPU

[Deepak S]

On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
> On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s at linux.intel.com wrote:
>> From: Deepak S <deepak.s at linux.intel.com>
>>
>> Based on the spec, Setting up static BIAS for GPU to improve the
>> rps performace.
>>
>> v2: rename reg defn to match spec. (Ville)
>>
>> v3: Updated bias setting for chv (Deepak)
>>
>> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> Matches the spec. Whether the chosen bias is really the best, I can't
> really say. But favoring the GPU does seem like a sensible idea if we
> want to keep the UI stuff fluid enough while there's some CPU heavy
> tasks running at the same time.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Thanks Ville for reviewing,
Yes our aim is to keep user experience smooth.

>> ---
>>   drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
>>   drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
>>   2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 36805b6..048987e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -670,6 +670,12 @@ enum skl_disp_power_wells {
>>   #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
>>   #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
>>   
>> +#define VLV_TURBO_SOC_OVERRIDE	0x04
>> +#define 	VLV_OVERRIDE_EN	1
>> +#define 	VLV_SOC_TDP_EN	(1 << 1)
>> +#define 	VLV_BIAS_CPU_125_SOC_875 (6 << 2)
>> +#define 	CHV_BIAS_CPU_50_SOC_50 (3 << 2)
>> +
>>   #define VLV_CZ_CLOCK_TO_MILLI_SEC		100000
>>   
>>   /* vlv2 north clock has */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 78c89ff..3689d0e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>   		   GEN6_RP_UP_BUSY_AVG |
>>   		   GEN6_RP_DOWN_IDLE_AVG);
>>   
>> +	/* Setting Fixed Bias */
>> +	val = VLV_OVERRIDE_EN |
>> +		  VLV_SOC_TDP_EN |
>> +		  CHV_BIAS_CPU_50_SOC_50;
>> +	vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
>> +
>>   	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>   
>>   	/* RPS code assumes GPLL is used */
>> @@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
>>   
>>   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
>>   
>> +	/* Setting Fixed Bias */
>> +	val = VLV_OVERRIDE_EN |
>> +		  VLV_SOC_TDP_EN |
>> +		  VLV_BIAS_CPU_125_SOC_875;
>> +	vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
>> +
>>   	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>   
>>   	/* RPS code assumes GPLL is used */
>> -- 
>> 1.9.1