[Intel-gfx] [PATCH 5/8] drm/i915/skl: Make the Misc I/O power well part of the PLLS domain

[Ville Syrjälä]

On Thu, Apr 30, 2015 at 04:39:20PM +0100, Damien Lespiau wrote:
> The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
> the PLLS power domain to ensure those two power wells are up.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>

Yep, spec does say that.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6188e94..5b0bce5 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -309,6 +309,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (		\
>  	SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |		\
> +	BIT(POWER_DOMAIN_PLLS) |			\
>  	BIT(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\
>  	(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\
> -- 
> 2.1.0
> 
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-- 
Ville Syrjälä
Intel OTC