[Intel-gfx] [PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[Imre Deak]

On ke, 2015-05-06 at 14:28 +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Do a POSTING_READ() between the DBUF_CTL register write and the
> udelay() to make sure we really wait after the register write has
> happened.
> 
> Spotted while reviewing Damien's SKL cdclk patch which had the
> POSTING_READ()s.
> 
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Yep, makes sense:
Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8e21e23..5c2047b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev)
>  	broxton_set_cdclk(dev, 624000);
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
>  	udelay(10);
>  
>  	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> @@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
>  	udelay(10);
>  
>  	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)