[Intel-gfx] [Mesa-dev] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.

[Chris Wilson]

On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
> > The BLT engine on Gen8+ requires linear surfaces to be cacheline
> > aligned.  This restriction was added as part of converting the BLT to
> > use 48-bit addressing.
> > 
> > intel_emit_linear_blit needs to handle blits that are not cacheline
> > aligned, as we use it for arbitrary glBufferSubData calls and subrange
> > mappings.
> > 
> > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
> > pixel X offset field to represent the unaligned portion, and subtract
> > that from the address so it's cacheline aligned.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
> > Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> > Cc: mesa-stable at lists.freedesktop.org
> 
> s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned
> that the hard way. Adding them to correct me in case I make a mess again.

It's cacheline.

Issue: if the 1st pixel in XY_SRC_COPY  is not CL aligned when SRC or
DST are linear that will cause failure.

https://vthsd.fm.intel.com/hsd/bdwgfx/bug_de/default.aspx?bug_de_id=1912704
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre