[Intel-gfx] [PATCH] drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Daniel Vetter]

On Wed, May 06, 2015 at 04:44:13PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2015 at 02:36:27PM +0100, Damien Lespiau wrote:
> > Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
> > 
> > Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
> > masked register. Re-oops.
> > 
> > A wonder if went through 2 people while having roughly a bug per line...
> > 
> > The problem was introduced in the original patch:
> > 
> >   commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
> >   Author: Damien Lespiau <damien.lespiau at intel.com>
> >   Date:   Mon Feb 9 19:33:20 2015 +0000
> > 
> >       drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
> > 
> > v2: Also fix the register write (Ville)
> > 
> > Reported-by: Robert Beckett <robert.beckett at intel.com>
> > Reported-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: Robert Beckett <robert.beckett at intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: Nick Hoath <nicholas.hoath at intel.com>
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 2 +-
> >  drivers/gpu/drm/i915/intel_pm.c | 3 +--
> >  2 files changed, 2 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5436ab0..6a1875a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5718,7 +5718,7 @@ enum skl_disp_power_wells {
> >  #define HSW_NDE_RSTWRN_OPT	0x46408
> >  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
> >  
> > -#define FF_SLICE_CS_CHICKEN2			0x02e4
> > +#define FF_SLICE_CS_CHICKEN2			0x20e4
> >  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> >  
> >  /* GEN7 chicken */
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 8812fff..e940a28 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -88,8 +88,7 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >  
> >  		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
> >  		I915_WRITE(FF_SLICE_CS_CHICKEN2,
> > -			   I915_READ(FF_SLICE_CS_CHICKEN2) |
> > -			   GEN9_TSG_BARRIER_ACK_DISABLE);
> > +			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
> >  	}
> >  
> >  	if (INTEL_REVID(dev) <= SKL_REVID_E0)
> > -- 
> > 2.1.0
> 
> -- 
> Ville Syrjälä
> Intel OTC
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch