[Intel-gfx] [PATCH 2/7] drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV

[Daniel Vetter]

On Fri, May 08, 2015 at 04:19:13PM +0300, Ville Syrjälä wrote:
> On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
> > 
> > 
> > On Friday 10 April 2015 08:51 PM, ville.syrjala at linux.intel.com wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index cfbd5a6..98588d5 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1887,7 +1887,10 @@ enum skl_disp_power_wells {
> > >   #define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)
> > >   #define   DPLL_PORTD_READY_MASK		(0xf)
> > >   #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
> > > -#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
> > > +#define   PHY_CH_SU_PSR				0x1
> > > +#define   PHY_CH_DEEP_PSR			0x7
> > 
> > PHY_CH_DEEP_PSR defined but not used in this patch?
> 
> Just wanted to define it since it's the only other valid value, and the
> doc situation is crap. I've not played around with PSR so I'm not
> entirely sure how these would be used in practise. My gut is telling me
> SU_PSR might be used with link standby and DEEP_PSR with link off, but
> that's just a hunch at this point.

Yeah adding all #defines in the a patch even if not all used is imo good
practice. Merged the first 3 patches to dinq, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch