[Intel-gfx] [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits

[Jani Nikula]

On Thu, 14 May 2015, Damien Lespiau <damien.lespiau at intel.com> wrote:
> gem_bad_blit.c: In function ‘bad_blit’:
> gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
>    OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  tests/gem_bad_blit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
> index 593167c..366b182 100644
> --- a/tests/gem_bad_blit.c
> +++ b/tests/gem_bad_blit.c
> @@ -60,7 +60,7 @@
>  static drm_intel_bufmgr *bufmgr;
>  struct intel_batchbuffer *batch;
>  
> -#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
> +#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */

Why not three pairs of braces? Or... *gasp* just one? ;)

Jani.

>  
>  static void
>  bad_blit(drm_intel_bo *src_bo, uint32_t devid)
> -- 
> 2.1.0
>
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-- 
Jani Nikula, Intel Open Source Technology Center