[Intel-gfx] [PATCH 3/4] drm/i915: Don't expose RGB/BGR 8888 formats on primary planes before SKL

[Ville Syrjälä]

On Fri, May 15, 2015 at 07:06:02PM +0100, Damien Lespiau wrote:
> We don't actually do anything different for the A version of the 8888
> RGB formats before SKL. Don't let user space think we can support alpha
> blending.

gen2/3 planes B/C, gen4 plane C, and all VLV/CHV primary planes might
support alpha, but yeah we don't program them that way currently. So
dropping it all first and then adding back as needed for each relevant
platform seems like the best approach.

> 
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++++++-----------
>  1 file changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5ebac76..c784f9a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -52,7 +52,6 @@ static const uint32_t i8xx_primary_formats[] = {
>  	DRM_FORMAT_XRGB1555,
>  	DRM_FORMAT_ARGB1555,
>  	DRM_FORMAT_XRGB8888,
> -	DRM_FORMAT_ARGB8888,
>  };
>  
>  /* Primary plane formats for gen >= 4 */
> @@ -61,6 +60,15 @@ static const uint32_t i965_primary_formats[] = {
>  	DRM_FORMAT_RGB565,
>  	DRM_FORMAT_XRGB8888,
>  	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +};
> +
> +static const uint32_t skl_primary_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
>  	DRM_FORMAT_ARGB8888,
>  	DRM_FORMAT_ABGR8888,
>  	DRM_FORMAT_XRGB2101010,
> @@ -2706,11 +2714,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		dspcntr |= DISPPLANE_BGRX565;
>  		break;
>  	case DRM_FORMAT_XRGB8888:
> -	case DRM_FORMAT_ARGB8888:
>  		dspcntr |= DISPPLANE_BGRX888;
>  		break;
>  	case DRM_FORMAT_XBGR8888:
> -	case DRM_FORMAT_ABGR8888:
>  		dspcntr |= DISPPLANE_RGBX888;
>  		break;
>  	case DRM_FORMAT_XRGB2101010:
> @@ -2812,11 +2818,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  		dspcntr |= DISPPLANE_BGRX565;
>  		break;
>  	case DRM_FORMAT_XRGB8888:
> -	case DRM_FORMAT_ARGB8888:
>  		dspcntr |= DISPPLANE_BGRX888;
>  		break;
>  	case DRM_FORMAT_XBGR8888:
> -	case DRM_FORMAT_ABGR8888:
>  		dspcntr |= DISPPLANE_RGBX888;
>  		break;
>  	case DRM_FORMAT_XRGB2101010:
> @@ -13278,12 +13282,15 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>  	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
>  		primary->plane = !pipe;
>  
> -	if (INTEL_INFO(dev)->gen <= 3) {
> -		intel_primary_formats = i8xx_primary_formats;
> -		num_formats = ARRAY_SIZE(i8xx_primary_formats);
> -	} else {
> +	if (INTEL_INFO(dev)->gen >= 9) {
> +		intel_primary_formats = skl_primary_formats;
> +		num_formats = ARRAY_SIZE(skl_primary_formats);
> +	} else if (INTEL_INFO(dev)->gen >= 4) {
>  		intel_primary_formats = i965_primary_formats;
>  		num_formats = ARRAY_SIZE(i965_primary_formats);
> +	} else {
> +		intel_primary_formats = i8xx_primary_formats;
> +		num_formats = ARRAY_SIZE(i8xx_primary_formats);
>  	}
>  
>  	drm_universal_plane_init(dev, &primary->base, 0,
> @@ -13961,7 +13968,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  	case DRM_FORMAT_C8:
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB8888:
> -	case DRM_FORMAT_ARGB8888:
>  		break;
>  	case DRM_FORMAT_XRGB1555:
>  	case DRM_FORMAT_ARGB1555:
> @@ -13971,8 +13977,15 @@ static int intel_framebuffer_init(struct drm_device *dev,
>  			return -EINVAL;
>  		}
>  		break;
> -	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (!IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 9) {

&&

With that fixed this is
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>


> +			DRM_DEBUG("unsupported pixel format: %s\n",
> +				  drm_get_format_name(mode_cmd->pixel_format));
> +			return -EINVAL;
> +		}
> +		break;
> +	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
>  		if (INTEL_INFO(dev)->gen < 4) {
> -- 
> 2.1.0
> 
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-- 
Ville Syrjälä
Intel OTC