[Intel-gfx] [PATCH i-g-t] gem_bad_blit: Make the BAD_GTT_TEST address more than 32 bits

[Daniel Vetter]

On Fri, May 15, 2015 at 10:09:34AM +0100, Chris Wilson wrote:
> On Thu, May 14, 2015 at 03:41:54PM +0100, Damien Lespiau wrote:
> > gem_bad_blit.c: In function ‘bad_blit’:
> > gem_bad_blit.c:89:3: warning: right shift count >= width of type [enabled by default]
> >    OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> > ---
> >  tests/gem_bad_blit.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
> > index 593167c..366b182 100644
> > --- a/tests/gem_bad_blit.c
> > +++ b/tests/gem_bad_blit.c
> > @@ -60,7 +60,7 @@
> >  static drm_intel_bufmgr *bufmgr;
> >  struct intel_batchbuffer *batch;
> >  
> > -#define BAD_GTT_DEST ((256*1024*1024)) /* past end of aperture */
> > +#define BAD_GTT_DEST ((256*1024*1024ULL)) /* past end of aperture */
> 
> Hmm, that comment and this test do not make sense. It has not been a bad
> blit since g33.

Yeah, I guess time to git rm gem_bad_blt. We have the hangman now to
exercise the reset/hang detection manchinery.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch