[Intel-gfx] [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A

[Damien Lespiau]

On Tue, May 19, 2015 at 03:39:25PM +0100, Damien Lespiau wrote:
> On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> > Also make the WA comment consistent with the rest, where the stepping
> > info is not shown.
> > 
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> >  1 file changed, 3 insertions(+), 6 deletions(-)
> > 
> > [ The patchset is a follow-up to:
> >   http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 9b96ed7..461b9be 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> >  			  GEN9_CCS_TLB_PREFETCH_ENABLE);
> >  
> > -	/*
> > -	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > -	 * the flag reads back as 0.
> > -	 */
> > -	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > -	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> > +	/* WaDisableMaskBasedCammingInRCC:skl,bxt */
> 
> For the record, there seem to be some confusion in the W/A db:
> 
>   - The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
>     and indeed there's a bit to do that, but the bug in question talks
>     about bit 14 of 7308, which is the disabling bit for the RCC unit
>   - The W/A isn't listed in the W/A db for BXT
> 
> In doubt, defaulting to trusting the spec and bug db is probably the
> saner option, so:
> 
> Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

Spoke too soon. This register is in the render context so has to be
written from the ring...

-- 
Damien