[Intel-gfx] [PATCH v3] drm/i915/skl: Deinit/init the display at suspend/resume

[Ville Syrjälä]

On Thu, May 21, 2015 at 04:49:40PM +0100, Damien Lespiau wrote:
> On Thu, May 21, 2015 at 06:44:53PM +0300, Ville Syrjälä wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index d602db2..cacb07b 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2510,6 +2510,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  	uint32_t val = I915_READ(LCPLL_CTL);
> > > +	int cdclk_freq;
> > >  
> > >  	if (IS_SKYLAKE(dev))
> > >  		skl_shared_dplls_init(dev_priv);
> > > @@ -2518,12 +2519,15 @@ void intel_ddi_pll_init(struct drm_device *dev)
> > >  	else
> > >  		hsw_shared_dplls_init(dev_priv);
> > >  
> > > -	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
> > > -		      dev_priv->display.get_display_clock_speed(dev));
> > > +	cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> > > +	DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
> > >  
> > >  	if (IS_SKYLAKE(dev)) {
> > > +		dev_priv->skl_boot_cdclk = cdclk_freq;
> > >  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> > >  			DRM_ERROR("LCPLL1 is disabled\n");
> > > +		else
> > > +			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> > 
> > Hmm, actually are we not calling the skl_init_cdclk() on boot at all? I see
> > it only in the resume path.
> 
> Yes that's correct, we always have display intialized by the firmware on
> big core as far as I know (which may not be true for BXT).

What about module reload?

-- 
Ville Syrjälä
Intel OTC